This invention relates to methods of defining at least two different field effect transistor channel lengths, to methods of forming a pair of field effect transistor channels having different channel lengths, to methods of forming a pair of field effect transistors having different channel lengths, and to integrated circuitry.
Integrated circuitry fabrication typically involves lithographic processing whereby a desired circuitry image is formed in an imaging layer. The image is transferred to underlying circuitry layers on a substrate by using the imaging layer as a mask during etching or other removal of underlying material exposed through the imaging layer. Further, in many instances it is desirable to form the same type of devices from a commonly deposited conductive layer to have different dimensions, including having different base widths of such devices.
Integrated circuitry fabricators are ever attempting to increase circuity density and thereby reduce the size of individual conductive components. As device dimensions decrease, interest is increasing in using alternatives to lithographic definition of features, particularly in an effort to achieve device dimensions that are smaller than the available, yet ever decreasing, minimum feature resolution using lithography.
Various vertical device structures are under investigations that make use of controlled deposition as a means of creating small features, with the base width dimension thereby being controlled largely by the deposition thickness of the layer. For example, it is possible to deposit conductive material over a vertical wall to a known desired thickness, and then remove it from horizontal surfaces by anisotropic reactive ion etching. This leaves a vertically extending conductive component having a base width essentially equal to the deposition thickness of the conductive layer. Such techniques have historically also been utilized to form insulative spacers over field effect transistor lines.
Further, in many instances it is desirable to form field effect transistors from commonly deposited conductive layers which have different designed channel lengths.
One way of accurately defining a single field effect transistor channel length is with respect to the deposition thickness of the channel layer itself which, if desired, can be sublithographic. One example of such processing in a device is described by Hergenrother et al. in an article entitled xe2x80x9cThe Vertical Replacement-Gate (VRG) MOSFET: A 50-nm Vertical MOSFET with Lithography-Independent Gate Lengthxe2x80x9d, of Bell Laboratories/Lucent Technologies. A copy of this document is submitted with an Information Disclosure accompanying the application which became this patent. Such discloses defining channel length by deposition of a channel defining layer through which an opening is etched, with the opening having opposing substantially vertical sidewalls. Semiconductive channel material then fills the opening. The channel defining layer is later removed and replaced with gate dielectric material and conductive gate material.
It would be desirable to improve upon this and other methods where channel defining layers are utilized for establishing gate length in field effect transistors.
The invention includes methods of defining at least two different field effect transistor channel lengths, to methods of forming a pair of field effect transistor channels having different channel lengths, to methods of forming a pair of field effect transistors having different channel lengths, and to integrated circuitry. In one implementation a method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths.
In one implementation, integrated circuitry includes a substrate having a mean global outer surface extending along a plane. A first field effect transistor has a first gate, a first gate dielectric layer, a first channel, and a pair of source/drain regions. One of the first transistor source/drain regions is received elevationally inward of the first channel, the other elevationally outward. The first field effect transistor has a first channel length defined along the first gate dielectric layer and has at least some portion which is substantially straight linear. A second field effect transistor has a second gate, a second gate dielectric layer, a second channel, and a pair of source/drain regions. One of the second transistor source/drain regions is received elevationally inward of the second channel, the other elevationally outward. The second field effect transistor has a second channel length defined along the second gate dielectric layer and has at least some portion which is substantially straight linear. The first and second channel lengths have different total lengths, both of the straight linear portions of the first and second channel lengths are angled from the plane, and at least one of the straight linear portions of the first and second channel lengths are beveled relative to the plane.